Compute-at-memory for highest throughput and lowest energy (and no off-chip DRAM required)
Pure Dataflow architecture for optimized data movement - streaming processing with low latency (Batch=1) and No Network on Chip (NoC) to maximize efficiency of data movement and reduce SW complexity
High Accuracy – Activations all use B-float (16-bit); (Choice of 4/8/16 bit Weights)
Scalability – Multiple small AI networks can run on one chip and large models can execute across multiple chips, all using the exact same SW
Deterministic – Consistent/precise execution times; SW simulation accurately matches HW measurements (frame rate, latency, etc.)
1 click model optimized compilation/ mapping of AI models “out of the box”
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