Recommended reasons:
1. End-to-End Automation: COPILOT auto-generates RTL, simulation models, compiler, and debugger components from custom instruction definitions, streamlining the EDA workflow.
2. Seamless Integration: All generated components integrate directly into Andes RISC-V development environments, reducing manual effort and time-to-market.
3. ACE Framework: Empowers designers to define, simulate, and implement custom instructions with ease, bridging hardware-software co-design in EDA flows.
4. Advanced Vector Support: ACE-RVV supports vector processors with scalable hardware for various data widths and custom types, accelerating high-throughput simulations.
5. AI-Ready Extensions: Supports BF16 and 4X widening/narrowing operations, enabling efficient modeling and analysis for AI and data-intensive designs.
6. Custom RTL Simulation: ACE allows direct integration of user-defined RTL into simulation flows, enhancing flexibility for architectural exploration.
7. Floating-Point DSP Design: ACE-Scalar supports floating-point register file access, streamlining design and verification of custom DSP instructions.
8. Area-Aware Optimization: The ACE-Scalar Engine features pipeline-level optimization, balancing simulation accuracy, area efficiency, and performance.
9. Functional Safety Support: With ACE integration in D23-SE, users can design safety-compliant (ISO 26262 ASIL B/D) instructions within a unified EDA flow.
Recommended reasons:
The Cadence® Conformal® AI Studio, which includes logical equivalence checking (LEC), automated functional engineering change order (ECO), and low-power static signoff products, both simplifies and accelerates the verification of complex SoC designs. It achieves this by leveraging re-architected scalable distributed core engines in concert with direct integrations to Cadence’s artificial intelligence (AI) and machine learning (ML) platforms.
For decades, Conformal technology has been a leader in the LEC subset of formal verification and remains the key auditor for ensuring digital implementation tools from both Cadence and third parties perform as intended. As designs have grown 100X in complexity over this timeframe, this task has intensified, and Cadence’s technology has evolved to meet design teams’ growing requirements.
Conformal AI technologies consist of a comprehensive next-generation suite that expands upon the legacy of the Conformal products and delivers four new enhancements for engineers: breakthrough productivity; power, performance, and area (PPA) enablement; ML-driven optimization; and AI-enabled analysis.
Conformal AI Studio includes three main products:
• Conformal AI Equivalence – Formal LEC
• Conformal AI ECO – Automated functional ECO generation
• Conformal AI Low Power – Low-power intent and static signoff
Recommended reasons:
Ansys RedHawk-SC is the industry’s trusted golden standard multiphysics signoff solution for power integrity and electromigration, tailored for digital designs. Its powerful analysis capabilities quickly identify potential weaknesses and support what-if scenario exploration to optimize both power and performance.
RedHawk-SC’s cloud-native architecture delivers the speed and capacity required for full-chip analysis. Its signoff accuracy is certified by all major foundries and supports all FinFET nodes down to 3nm.
Recommended reasons:
The semiconductor industry requires robust and energy-efficient data center infrastructure and Electronic Design Automation (EDA) solutions to continuously develop next-generation chips. AMD EPYC™ 9005 Series processors, the world's most powerful server CPUs, deliver record-breaking performance and efficiency, along with industry-leading features, for enterprise computing, AI, cloud, and other data center workloads.
AMD EPYC 9005 Series processors feature up to 192 "Zen 5" or "Zen 5c" cores, 12 channels of DDR5 memory per CPU supporting up to DDR5-6400 MT/s, and a large L3 cache of up to 384MB. They also offer industry-leading boost frequencies of up to 5GHz and AVX-512 with a full 512b data path. Among these, the high-frequency SKUs up to DDR5-6400 MT/s help users achieve desired performance with fewer cores, thereby optimizing power consumption and Total Cost of Ownership (TCO), while the large L3 cache of up to 384MB is a key driver for EDA performance. Furthermore, the innovative AMD chiplet architecture enables efficient and energy-saving solutions that meet diverse computing needs.
Compared to "Zen 4" cores, "Zen 5" cores deliver up to a 17% IPC uplift for enterprise and cloud workloads, and up to a 37% IPC uplift for AI and high-performance computing. The EPYC 9005 Series is an industry-leading AI processor. Compared to the competitor's top 64-core Intel Xeon 8592+ processor, the 192-core AMD EPYC 9965 processor provides maximized performance per server (up to 60% fewer servers, 40% less power consumption, and 41% lower 3-year TCO for the same integer performance), leading AI inference performance (up to 3x inference throughput), and maximizes graphics card acceleration (the 64-core EPYC 9575F delivers up to 20% system performance improvement).
Recommended reasons:
Generative Al
GAN
Diffusion Model
WAT Super Resolution (WAT-SR)
High-Efficiency SPICE-Silicon Bias Modeling (He-SSBM)
High-Fidelity Generative Monte Approximation (HΣ-GMA)
Multivariate Normal Distribution
Recommended reasons:
iSTART-TEK has successfully obtained the U.S. patent for “METHOD FOR GENERATING A MEMORY BUILT-IN SELF-TEST ALGORITHM CIRCUIT”! iSTART-TEK’s self-developed User-Defined Algorithm (UDA) adopts the architecture outlined in this patent.
Commonly used memory testing algorithms on the market currently exhibit behaviors of repetitive testing, requiring additional testing time and costs. Simultaneously, with the continuous evolution of technology, advanced manufacturing processes are consistently emerging. Existing algorithms may not be capable of detecting memory defects in these advanced processes, failing to meet the demands of staying up-to-date.
iSTART-TEK’s new patent can effectively addresses this situation. By utilizing UDA, redundant elements can be eliminated. Users can edit algorithm files, define memory locations, significantly reducing memory testing time. Additionally, UDA allows the design of more complex and area-efficient memory testing algorithms, offering greater flexibility and diversity.
After obtaining a Taiwanese patent in 2022, this technology successfully secured a U.S. patent in October 2023. This not only acknowledges iSTART-TEK’s research and development capabilities but also instills confidence in its ability to assist customers in resolving memory testing challenges and improving design and production efficiency.
Recommended reasons:
REDEXPERT is Würth Elektronik’s advanced online simulation platform designed to streamline the design process of power electronics and EMC filtering. Built on real laboratory measurements—not theoretical models—it enables engineers to select, compare, and simulate components with the highest level of precision.
REDEXPERT covers over 36 component families with more than 20 real-time application simulations, all accessible without registration or installation. It allows interactive comparison of inductors by current vs. inductance, and temperature rise vs. DC current. Its EMI filter designer—a web-first innovation—helps users design custom filters by setting electrical and mechanical parameters to meet application-specific requirements.
Key highlights:
• No installation required; web-based and mobile-friendly
• 6 languages supported, ensuring global accessibility
• Accurate AC/DC loss simulation for inductors in DC/DC converters
• EMI filter simulation tool with recommendations based on user input
• Free sample ordering directly from the platform
• Continuously updated with new modules and application types
By integrating real-world data and intuitive design workflows, REDEXPERT not only accelerates product development but also enhances design confidence for engineers working on power integrity and EMC compliance.
Malicious vote manipulation is expressly forbidden in this voting event. The organizers reserve the right to evaluate the fairness and accuracy of the voting results. AspenCore retains the authority to interpret the rules of this event.